Prior art semiconductor devices have a semiconductor chip mounted on a printed wiring board and generally employ a wire bonding connection with which the terminals on the semiconductor chip and the terminals on the printed wiring board are connected by bonding wires or a flip chip connection with which Au or solder bumps are formed on the terminals on the semiconductor chip and the bumps and the terminals on the printed wiring board are connected.
In addition to the above structure, semiconductor devices using a printed wiring board in which a semiconductor chip is embedded face-down, namely with the surface of the the semiconductor chip on which the connection terminals are formed (the circuit surface) facing down, have been proposed. Patent Literature 1 and Prior Application 1 (Patent Application No. 2006-300681) describe a semiconductor device in which a semiconductor chip is embedded in a printed wiring board and the wiring layers are formed on the semiconductor chip circuit surface side. Patent Literature 2 and Prior Application 2 (Patent Application No. 2007-093083) describe a semiconductor device in which a semiconductor chip is also embedded in a printed wiring board and the wiring layers are formed on both sides of the semiconductor chip, namely on the circuit surface side and on the rear surface side where no connection terminal is formed.
In the above semiconductor devices, an assembly process involving wire bonding or flip chip connection is unnecessary. The connection terminals of the semiconductor chip can be connected to the terminals on the printed wiring board in the printed wiring board production process. Therefore, reduction in assembly cost is highly expected.
Furthermore, the aforementioned printed wiring board can be a built-up board, which allows for wires and vias with fine pitch. Consequently, the printed wiring board can be downsized and the semiconductor device can accordingly be downsized. In addition, there is an expectation of application to semiconductor chips having more pins with a finer pitch than the semiconductor devices produced by a flip chip connection.
Although a built-up board allows for finer wires, the wiring layers must be formed one by one. It is known that the yield drops by a factor of the factorial of the number of layers as the number of layers is increased. Therefore, manufacturing quality is not ensured in the production of semiconductor devices having a printed wiring board in which a semiconductor chip is embedded unless the product has a small number of layers.
Meanwhile, some semiconductor chips have an area terminal consisting of terminals arranged in a matrix on the circuit surface and some have a peripheral terminal consisting of terminals arranged in a row on the circuit surface. For producing a semiconductor device using a semiconductor chip with an area terminal, a specific number of layers corresponding to the number of matrixes are necessary for pulling out all wires in the printed wiring board. Therefore, a multilayer printed wiring board having four or more layers is generally used. Furthermore, the above semiconductor device is produced by connecting a semiconductor chip having an area terminal to a multilayer printed wiring board by means of a flip-chip connection. The terminals arranged in a matrix cannot be connected to terminals arranged in one or two rows on a printed wiring board one by one by wire bonding.
Problems with embedding the above semiconductor chip having an area terminal in a multilayer printed wiring board include the fact that the number of built-up layers is increased, yield drops, and manufacturing quality is not ensured when the multilayer printed wiring board has four or more layers, as in the prior art.
Patent Literature 1 and 2 and Prior Applications 1 and 2 disclose the structures for embedding a semiconductor chip in a printed wiring board and the methods for producing them. However, there is no disclosure regarding the specific design of wiring patterns such as specific assignment of wiring layers to signal wires, power wires or a power plane, or ground wires or a ground plane and assignment schemes for reducing the number of layers.
Patent Literature 3 describes a semiconductor device in which a semiconductor chip having a peripheral terminal is embedded in a printed wiring board and the layer structure is designed to reduce the number of layers of the printed wiring board.
Patent Literature 1: Unexamined Japanese Patent Application KOKAI Publication No. 2003-46019;
Patent Literature 2: Unexamined Japanese Patent Application KOKAI Publication No. 2003-309243; and
Patent Literature 3: Unexamined Japanese Patent Application KOKAI Publication No. 2005-228901.